1. Field of the Invention
The present invention relates to a semiconductor device process, more specifically, to a method for forming bit line contact hole/contact structure.
2. Description of the Prior Art
In the manufacturing process for DRAM, forming a bit line contact structure between two word line structures is a common procedure.
FIG. 1 is a schematic structure diagram showing a bit line contact hole formed between two word line structures. In the drawing, reference number 10 indicates a silicon substrate, 12 indicates a word line structure formed on the silicon substrate 10. In current process, each word line structure 12 generally comprises a conductive portion having a metal layer 121 (of which the material can be WSi) and a poly-silicon layer 123, and a protective layer 13. Generally, the material of the protective layer 13 is nitride, such as SiN. The protective layer 13 is formed to cover the conductive portion of the word line structure and also cover the whole silicon substrate with a thin layer, as shown in the drawing. Then, a first dielectric layer 14, of which the material is generally BPSG, is formed on the whole structure. Considering of strain problem, a second dielectric layer 16 is formed on the first dielectric layer 14. The material of the second dielectric layer 16 is generally oxide without being doped with dopant selected from group III or V, such as TEOS.
Dry etch is used to remove the selected position of the TEOS layer and BPSG layer to form a bit line contact hole 18. Due to the property of the etchant, such an etching process will stop at the SiN layer, as shown in FIG. 1. Then the SiN portion at the bottom of the contact hole 18 is removed to make an access to the silicon substrate. This process is generally referred to SAC (self-aligned contact hole) etching. Among current SAC etching techniques, RIE (reactive ion etching) combining a physical etching (for verticality of the etched profile) and a chemical etching (for etch selectivity) is the most widely used. In this method, the etching is performed by chemical action and ion bombard.
However, as DRAM becomes more compact, the critical dimensions of various structures including the bit line contact structure is required to be compressed. In other words, the critical dimension of the contact hole becomes smaller and smaller. Under such circumstances, the chemical action in the etching process usually fails to clearly remove the predetermined portion of the dielectric layers (TEOS and BPSG), and therefore the assistance of the physical process (i.e. the ion bombard) is necessary. However, enhancing the ion bombard to remove the predetermined portion of the dielectric layers often damages shoulder portions 19 of the word line structure, as shown in FIG. 1. When the protective layer at the shoulder portion 19 is damaged to a certain degree, the conductive layer under the protective layer will be exposed. Under such circumstances, when the bit line contact hole is filled with metal to form a bit line contact structure, improper short circuit will happen to the bit line and the word line, which will be formed later.
Therefore, there is a need for a solution to overcome the problem stated above. The present invention satisfies such a need.